Compared to the devices typical of the telecom revolution of two decades ago, today’s typical Silicon Photonics (SiP) devices present more channels, smaller form factors, and exponentially higher production quantities. Transverse alignment tolerances well below 50nm are common, and multi-channel inputs and outputs necessitate at least an additional theta-Z alignment in order to optimize and balance the couplings across the input or output array. Very often the theta-X and theta-Y orientations must be optimized as well, and Z gaps must be set by vision or by contact sensing, or by a waist-seeking approach in lensed applications.
These multiple degree-of-freedom alignments confront the engineer with vexing geometrical interactions, such as de-alignments in X and Y when an angular adjustment is performed about an imperfectly-placed pivot point. And today’s short SiP waveguides often exhibit a steering phenomenon, where adjustments of the input coupling result in deflections of the optimum coupling at the output, rendering the overall alignment a moving target. Together, these properties have traditionally necessitated a looping, iterative approach to converge on a global optimization— a very time-consuming process.
PI’s Fast Multichannel Photonics Alignment (FMPA) engines integrate novel, firmware-based algorithms that allow multiple linear and angular digital gradient search alignments to be performed simultaneously, in parallel. Each gradient search provides efficient, repeatable alignment on its own, but with FMPA, a global optimization across all the inputs, outputs, and degrees of freedom can reduce to one quick step. Alignment-process throughput improvements exceeding 1- to 2-orders of magnitude are commonplace versus previous alignment technologies.
A Live Demo for Thousands
PI continued with its tradition of addressing a challenging application on the conference floor at 2017’s teeming Photonics West. Spotlighted in the booth was a head-turning array alignment application that deployed a six-degree-of-freedom H-811 hexapod and a P-616 Nanocube to align two fiber arrays.
The key to this application was the parallel execution of angular and transverse alignments. The Nanocube performed a transverse gradient search with tracking to lock-onto the first channel of the array, while the hexapod performed a theta-Z gradient search on the Nth channel of the array. The hexapod’s commandable pivot point allowed the rotational centerpoint to be placed very close the optical axis of the first array element. The Nanocube’s XY lock-on compensated for the small residual transverse runout due to imperfections in localizing the optical axis.
The system then went about its business of repetitively de-aligning and re-aligning the array as attendees watched. The whole process only took a few seconds, including delays inserted to assist visualization. Animating the process was a user-friendly, scriptable GUI constructed from PI’s extensive software libraries, which provide cross-platform support of many popular programming languages. A test executive was then constructed in Python to automate the operation of the GUI (MATLAB has also been popular for this), allowing many thousands of faultless alignments to be performed for visitors to the booth.
A Unique, Fab-Class Architecture
FMPA is based on 100% closed loop digital technology, virtually eliminating drift when not tracking. Besides the parallel gradient search capability, the controller firmware includes rapid areal scanning with automatic fitting for centroid determination, allowing fast, robust alignment of challenging couplings like top-hats.
FMPA systems are based on a 100x100x100µm travel compact XYZ “Nanocube” nanopositioner, offering 25X the capture area of typical alignment hardware. In most applications, the Nanocubes are mounted on high-performance long-travel stages or on compact, high-resolution 6-degree-of-freedom hexapods, depending on whether or not the devices being aligned require angular optimization.
An Industry Enabler
FMPA is a uniquely fast, capable, flexible, and precise architecture that has been deployed throughout the SiP production chain, from wafer test to packaging automation and intermediate chip-level tests. Its unique, firmware-based parallel capabilities enable one-step global optimization across multiple channels and degrees of freedom, representing a truly enabling technology that can speed time-to-market and ensure the profitable manufacture of silicon photonics devices.